In general, broadband communications are high-speed (e.g., greater than 45 megabits-per-second) data transmissions within a wide area network (WAN). Although typically broadband communication systems are fiber optic in nature, other media, such as coax cables, twisted pairs and serial backplanes are sometimes used. For example, many broadband networks include fiber optic interfaces that are constructed in accordance with the SONET (Synchronous Optical NETwork) standard. As is known, SONET is an optical interface standard that allows internetworking of transmission products from multiple vendors and prescribed transmission rates from 51.84 megabits-per-second to over 10 gigabits-per-second.
Other standards and protocols employing switching techniques that can vastly differ from the SONET standard are also known. For example, serial backplanes are not regulated by any standard, resulting in the existence of many proprietary signaling/switching schemes to improve the performance and costs of serial backplane systems. Further, timing recovery circuits are typically not protocol agnostic and rely on transition density to solve the problem of timing recovery. The reliance on transition density of prior art timing recovery circuits can lead to improper data sampling because of timing inaccuracy resulting from drifting and loss of synchronization due to low update rates during transitionless data periods.
As is also known, data transmissions via fiber optic and other data links are serial streams of data, but within a network component (e.g., switch, relay, bridge, gateway, et cetera) the data is processed in parallel. As such, each network component typically includes a serializer-deserializer transceiver (i.e., transmitter and receiver). In general, the transmitter converts parallel data into serial data and sources the serial data onto a fiber optic link. A receiver receives serial data via a fiber optic link and converts it back into parallel data.
A critical function of the receiver is to sample accurately the received serial data to be able to produce the parallel data. While the data rates for, for example, fiber optic transmissions are specified, and hence the required clock signals are specified, the clocks of the transceivers are not synchronized. Thus, the phase and/or frequency of the transmitter sourcing the received serial data may not align with the clock signal of the receiver. Such a misalignment, if uncorrected, can produce errors in the resulting parallel data. To correct the misalignment, receivers include a data and clock recovery circuit.
In general, timing recovery circuits and methods can be divided into two categories: phase-locked loop (PLL) architecture based timing recovery, and delay-locked loop (DLL) architecture based timing recovery. FIGS. 1 and 2, respectively, are block diagrams of PLL and DLL based timing recovery circuits that are widely used in various types of communication systems, including fiber optic networks.
As shown in FIG. 1, the PLL based timing recovery scheme can employ a data-driven phase detector, a loop filter, a voltage controlled oscillator (VCO), and an optional divider module. The data-driven phase detector produces an output signal that is a measure of the phase/timing difference of its inputs: a data input signal and a feedback clock. The output of the phase detector is filtered through the loop filter to generate a control voltage for the voltage controlled oscillator (VCO). The VCO is a controlled frequency source that produces an output oscillation based on the control voltage. The output oscillation can then be divided down by n (where n is any positive number) in the divider module to produce the feedback clock signal. The rate of the output oscillation is based on the divider module value such that if the divider module value is one, then the rate of the output oscillation is equal to the rate of the data input signal, and if the divider module value is two, the rate of the output oscillation is twice that of the data input signal, etc. As will be appreciated by one of average skill in the art, an auxiliary frequency acquisition loop can be used to aid the VCO in pulling close to the data rate. For example, the feedback clock signal, synchronized with the timing of the data input signal, can be used to retime the data input signal for processing and switching as needed in a communications system implementing the timing recovery scheme.
In the DLL based timing recovery scheme of FIG. 2, a delay cell replaces the VCO of FIG. 1. The delay cell introduces an adjustable delay to its input reference clock by means of the control voltage signal. A conceptual diagram of a delay cell based on phase interpolation, as known to those familiar with the art, is shown in FIG. 3.
As shown in FIG. 3, a phase interpolator employs several fixed clock phases (e.g., 0°, 90°, 180°, 270°) to create an adjustable phase. For example, the phase interpolator can produce 16 phases of a reference clock with steps corresponding to 360° divided by 16. The selection of a particular phase is based on the enablement of switches D0–D15. As is also shown, each switch controls a current source that when enabled couples the current source to the output (e.g., the recovered clock signal) via a transistor. For example, if the desired phasing of the recovered clock signal is 0°, switches D0–D3 are enabled and the remaining switches are disabled. For a phase shift of 360° divided by 16, switches D1–D4 are enabled while D0 and D5–D15 are disabled. Accordingly, each phase step is achieved by enabling various combinations of the switches.
In both PLL and DLL based timing recovery systems, the accuracy and timeliness of the phase detector output plays a significant role in performance. Because both PLL and DLL based timing recovery circuits are closed loop feedback circuits, when the phase detector updates diminish (i.e., the data input is a relatively long string of zeros or ones), they tend to drift and lose the synchronization with the data input signal. In addition, drifting and loss of synchronization introduces jitter in the feedback clock signal which degrades the data retiming and causes bit errors. These transitionless, relatively long strings of zeros or ones, are of concern for both full-rate and half-rate timing recovery circuits. FIG. 4 illustrates examples of data and clock timing relationships for full-rate and half-rate timing recovery schemes.
FIG. 5 shows a schematic block diagram of a prior art half-rate binary type phase detector combined with a loop filter. As a result of sampling a data input signal with four equally spaced phases (e.g., 0, 90, 180 and 270 degrees) of the feedback clock, XOR (exclusive OR) outputs A, B, C and D indicate whether the feedback clock is late or early with respect to a desired sampling instant of the data input signal. The decision logic within the phase detector processes the XOR outputs to generate a valid late/early decision, which is used to update the timing recovery loop. A digital loop filter having high noise immunity can be used to filter the late/early signal, which is particularly advantageous in highly integrated systems. In addition, use of a digital loop filter eliminates bulky RC components, which can vary due to IC manufacturing process variations and temperature, allowing for the flexible and accurate realization of large time constants in a relatively small silicon area. Decimation (sub-sampling) is widely used in digital filters to adjust the corner frequency of the filters and obtain large time constants.
The phase detector XOR outputs produce a late/early decision on every feedback clock period, while the digital loop filter accepts a decision on every Mth period of a reference clock. If the optional divider module previously discussed with respect to FIGS. 1 and 2 is a divide by 1 divider, the feedback clock and the reference clock will be the same frequency. As will be recognized by those skilled in the art, the low pass bandwidth of the timing recovery system should be decades smaller than the data rate of concern. Therefore, M values ranging from the 10's to 100's can be possible and may be required. As a result, long transitionless periods of the data input signal combined with large decimation by M in the digital loop filter cause update inaccuracies that degrade the timing recovery performance.
FIGS. 6 and 7 provide an example timing diagram and decision table, respectively, for the phase detector and digital loop filter timing recovery circuit of FIG. 5. FIG. 8 shows a block diagram of a prior art implementation of the decision logic for the same circuit. FIGS. 9a and 9b, respectively, depict a current mode logic (CML) structure for an XOR gate as a transistor-level schematic and as a conceptual symbol. The CML structure XOR gate of FIGS. 9a and 9b is used in FIG. 10, which provides a schematic block diagram of an analog implementation of the decision logic of the phase detector of FIG. 5 combined with a digital loop filter. During long transitionless periods of the data input signal, the analog implementation of FIG. 10 suffers various problems, including leakage through the RC components, comparator offset and improper sampling due to timing inaccuracy. FIG. 11 illustrates the comparator input node signals during a long transitionless period for the analog implementation timing recovery circuit of FIG. 10.
During high transition density periods, large RC time constants decrease the effect of comparator offset and improper sampling instances because they average toward the correct direction for phase alignment among many decisions per every transition. This is because a few inaccurate decisions among many decisions cannot have a significant impact. FIG. 12 is a timing diagram illustrating the latency and inaccuracy introduced due to the comparator offset for the analog implementation of FIG. 10.
Another problem associated with the prior art timing recovery circuit of FIG. 10 is the inability to determine whether a valid data transition has occurred. This can cause incorrect decisions at the comparator output when there is no transition, resulting in drift of the clock and data alignment. As an improvement to the analog implementation of FIG. 10, another comparator can be used to flag the data input signal transitions by means of a transition detect signal. FIG. 13 is a schematic block diagram of an analog implementation of a phase detector decision logic incorporating a second comparator for detecting data input signal transitions. FIG. 14 illustrates an example timing diagram for the phase detector of FIG. 13. This phase detector can be thought of as a 3-state phase detector where “late”, “early”, and “no transition” are the states and the “late/early” and “transition” output signals are used to switch between the states.
The prior art phase detector of FIG. 13, however, can still fail to detect single transitions between long transitionless periods of the data input signal due to comparator offset and improper sampling instants. FIG. 15 illustrates another example timing diagram for the phase detector of FIG. 13 illustrating that due to phase differences between the feedback clock and the reference clock, late/early signal pulses and transition output signal pulses can be missed. Comparator offsets can further shrink the pulse width of the late/early signal and the transition output signal. Failure to detect a single isolated data input signal transition could be a fatal problem for a timing recovery circuit.
Instead of using a divide by M version of the reference clock, the reference clock itself could be used to sample the phase detector output, and loop update can be achieved at almost the same rate of the feedback clock. As will be realized by one of average skill in the art, however, this will not eliminate the problem associated with an isolated single data transition, because unknown phase differences between the feedback clock and the reference clock still exist. Further, such a design would require supplying significantly more power to the digital loop filter due to increased operating frequency.
Therefore, a need exists for a data and clock recovery circuit for use in digital communication systems that can reduce or eliminate these problems of the prior art.